1. Field of the Invention
The present invention relates to a semiconductor memory system.
2. Description of the Related Art
FIG. 10 illustrates a flash memory 1 representing a semiconductor memory system in the prior art. This flash memory 1 stores information by varying the threshold voltage of the MOSFETs constituting individual memory cells. The threshold voltage of a MOSFET is adjusted by injecting electrons into a floating gate 13 provided between a tunnel oxide film 11 and an insulating film 12 and constituted of poly-crystalline silicon and drawing electrons from the floating gate 13.
Under normal circumstances, an F-N (Fowler-Nordheimt) tunnel current is generated at the tunnel oxide film 11 by applying a specific electrical field to the tunnel oxide film 11 or channel hot electrons that pass through the tunnel oxide film 11 are generated by engaging the MOSFET in operation, to inject electrons into the floating gate 13.
Electrons are drawn out from the floating gate 13, on the other hand, by using an F-N tunnel current between the drain and the floating gate 13 or an F-N tunnel current between the floating gate 13 and a P-type substrate 21.
However, the flash memory 1 in the prior art necessitates a high voltage to be applied to the tunnel oxide film 11 in order to ensure that a sufficient F-N tunnel current is applied to the tunnel oxide film 11 during a data write/erase operation at the memory cell.
In addition, positive holes are also injected into the floating gate 13 as electrons are injected into the floating gate 13 by using an F-N tunnel current. As data are overwritten repeatedly, the difference between the threshold voltage for a data write and the threshold voltage for a data erase becomes smaller, posing the risk of an erroneous data write/read.
It is necessary to fully turn on the MOSFET to inject electrons into the floating gate 13 by generating channel hot electrons, and even then, only so-called lucky hot electrons in the channel, are actually injected. As a result, the injection in efficiency with which electrons are injected relative to the current is low, causing difficulty in achieving a reduction in the power consumption at the flash memory 1.
In addition, the following problem is yet to be addressed in the flash memory 1 in the prior art with regard to system scale reduction. The coupling rate of the electrostatic capacity between the substrate 21 and the floating gate 13 and the electrostatic capacity between the floating gate 13 and a control gate 15 constituted of poly-crystalline silicon is a crucial factor in obtaining the electrical field necessary to supply a sufficient F-N tunnel current to the tunnel oxide film 11. In more specific terms, an electrostatic capacity which is sufficiently large relative to the electrostatic capacity between the substrate 21 and the floating gate 13 must be assured between the floating gate 13 and the control gate 15. Consequently, it is difficult to reduce the memory cell size by minimizing the area occupied by the floating gate 13.
An object of the present invention, which has been completed by addressing the problems discussed above, is to provide a semiconductor memory system which makes it possible to reduce the memory cell size, prevent an erroneous data write/read and achieve a reduction in power consumption.
In order to achieve the object described above, in a first aspect of the present invention, a semiconductor memory system having a plurality of memory cells and a decoder that selects one or more memory cells from the plurality of memory cells is provided. The individual memory cells provided in the semiconductor memory system each comprise a channel portion constituted of a semiconductor, a source portion constituted of a semiconductor, a drain portion constituted of a semiconductor, a control gate portion and a floating gate portion that is in an electrically suspended state between the channel portion and the control gate portion. In the semiconductor memory system in which one or more memory cells are selected from the plurality of memory cells by the decoder, a reference voltage is applied to the source portion, the reference voltage is applied to the drain portion, a first voltage at a level higher than the level of the reference voltage is applied to the control gate portion and a second voltage at a level higher than the level of the reference voltage and lower than the level of the first voltage and a third voltage at a level lower than the level of the reference voltage are alternately applied to the channel portion at each selected memory cell.
In the semiconductor memory system structured as described above, in which the channel portion, the source portion and the drain portion of a selected memory cell may be respectively constituted of a P-type semiconductor, an N-type semiconductor and an N-type semiconductor, the pn junction formed by the drain portion and the channel portion enters a foreword bias state when the second voltage is applied to the channel portion, and, as a result, electrons are injected into the channel portion from the drain portion. When the third voltage is applied to the channel portion, the pn junction formed by the source portion and the channel portion and the pn junction formed by the drain portion and the channel portion both enter a reverse bias state, which results in a depletion layer manifesting at the channel portion. The electrons in the channel are accelerated at the depletion layer and move into an insulated area located between the channel portion and the floating gate portion. In addition, when the third voltage is applied to the channel portion, an electrical field is generated between the floating gate portion and the channel portion by the potential difference between the control gate portion and the channel portion. This electrical field causes the electrons, which have moved into the insulated area between the channel portion and the floating gate portion to become injected into the floating gate portion. It is to be noted that if the channel portion, the source portion and the drain portion are respectively constituted of an N-type semiconductor, a P-type semiconductor and a P-type semiconductor, positive holes are injected into the channel portion to travel to the floating gate portion.
In the semiconductor memory system m a second aspect of the present invention, in which one or more memory cells are selected by the decoder from the plurality of memory cells, a reference voltage is applied to the source portion, a fourth voltage at a level higher than the level of the reference voltage is applied to the control gate portion, a fifth voltage at a level lower than the level of the reference voltage is applied to the channel portion and a sixth voltage at a level lower than the level of the fifth voltage is applied to the drain portion at each selected memory cell.
In the semiconductor memory system structured as described above, the pn junction formed by the drain portion and the channel portion enters a foreword bias state at a selected memory cell and, as a result, electrons are injected into the channel portion from the drain portion. The pn junction formed by the source portion and the channel portion on the other hand, enters a reverse bias state, which results in a depletion layer manifesting at the channel portion. The electrons in the channel are accelerated at the depletion layer and move into an insulated area located between the channel portion and the floating gate portion. In addition, an electrical field is generated between the floating gate portion and the channel portion by the potential difference between the control gate portion and the channel portion. This electrical field causes the electrons, which have moved into the insulated area between the channel portion and the floating gate portion, to become injected into the floating gate portion.
In addition, in the semiconductor memory system according to the present invention, in which there is one or more unselected memory cells that have not been selected by the decoder among the plurality of memory cells, a seventh voltage is applied to the control gate portion and the channel portion of each unselected memory cell. Since no potential difference manifests between the control gate portion and the channel portion at an unselected memory cell in the semiconductor memory system, no electrical field is generated between the floating gate portion and that channel portion. Thus, injection of electrons into the floating gate portion of an unselected memory cell is prevented. In addition, by roughly equalizing the level of the seventh voltage to the level of the fifth voltage, a common source can be utilized.
Alternatively, in the semiconductor memory system according to the present invention in which there is one or more unselected memory cells that have not been selected by the decoder among the plurality of memory cells, an eighth voltage at a level equal to or higher than the level of the voltage applied to the channel portion is applied to the drain portion of each unselected memory cell. Since the pn junction between the drain portion and the channel portion is set in an unbiased state or a reverse bias state at an unselected memory cell in this semiconductor memory system, electrons are not injected from the drain portion into the channel portion. As a result, injection of electrons into the floating gate portion is prevented at the unselected memory cell. In addition, by roughly equalizing the level of the eighth voltage to the level of the reference voltage, a common source can be utilized.
In the semiconductor memory system in a third aspect of the present invention, in which one or more memory cells are selected by the decoder from the plurality of memory cells, a ninth voltage at a level higher than the level of the reference voltage is applied to the control gate portion, a tenth voltage at a level lower than the level of the reference voltage is applied to the channel portion, an eleventh the voltage at a level lower than the level of the tenth voltage and the reference voltage are alternately applied to the source portion and a twelfth voltage at a level lower than the level of the tenth voltage and the reference voltage are alternately applied to the drain portion at each selected memory cell.
In the semiconductor memory system adopting the structure described above, when the eleventh voltage is applied to the source portion at a selected memory cell, the pn junction formed by the source portion and the channel portion enters a forward bias state and, as a result, electrons are injected into the channel portion from the source portion. Likewise, when the twelfth voltage is applied to the drain portion at the selected memory cell, the pn junction formed by the drain portion and the channel portion enters a forward bias state and, as a result, electrons are injected into the channel portion from the drain portion. When the reference voltage is applied to the source portion and the drain portion, the pn junction formed by the source portion and the channel portion and the pn junction formed by the drain portion and the channel portion both enter a reverse bias state, resulting in a depletion layer manifesting at the channel portion. The electrons in the channel are accelerated at the depletion layer and move into an insulated area located between the channel portion and the floating gate portion. In addition, an electrical field is generated between the floating gate portion and the channel portion by the potential difference between the control gate portion and the channel portion. This electrical field causes the electrons that have moved to into the insulating area between the channel portion and the floating gate portion to be injected into the floating gate portion.
In the semiconductor memory system in a fourth aspect of the present invention, in which one or more memory cells are selected by the decoder from the plurality of memory cells, a thirteenth voltage at a level higher than the level of the reference voltage is applied to the control gate portion, a fourteenth voltage at a level lower than the level of the reference voltage is applied to the channel portion, the reference voltage is applied to the source portion and a fifteenth voltage at a level lower than the level of the fourteenth voltage and the reference voltage are alternately applied to the drain portion at each selected memory cell.
In the semiconductor memory system adopting the structure described above, when the fifteenth voltage is applied to the drain portion at a selected memory cell, the pn junction formed by the drain portion and the channel portion enters a forward bias state and, as a result, electrons are injected into the channel portion from the drain portion. When the reference voltage is applied to the drain portion, the pn junction formed by the source portion and the channel portion and the pn junction formed by the drain portion and the channel portion both enter a reverse bias state, resulting in a depletion layer manifesting at the channel portion. The electrons in the channel are accelerated at the depletion layer and move into an insulated area located between the channel portion and the floating gate portion. In addition, an electrical field is generated between the floating gate portion and the channel portion by the potential difference between the control gate portion and the channel portion. This electrical field causes the electrons that have moved to into the insulating area between the channel portion and the floating gate portion to be injected into the floating gate portion.
In addition, in the semiconductor memory system according to the present invention, in which there is one or more unselected memory cells that have not been selected by the decoder among the plurality of memory cells, a sixteenth voltage is applied to the control gate portion and the channel portion of each unselected memory cell. Since no potential difference manifests between the control gate portion and the channel portion at an unselected memory cell in the semiconductor memory system, no electrical field is generated between the floating gate portion and that channel portion. Thus, injection of electrons into the floating gate portion of the unselected memory cell is prevented. In addition, by roughly equalizing the level of the sixteenth voltage to the level of the fourteenth voltage, a common source can be utilized.
Alternatively, in the semiconductor memory system according to the present invention in which there is one or more unselected memory cells that have not been selected by the decoder among the plurality of memory cells, a seventeenth voltage at a level equal to or higher than the level of the voltage applied to the channel portion is applied to the drain portion of each unselected memory cell. Since the pn junction between the drain portion and the channel portion is set in an unbiased state or a reverse bias state at an unselected memory cell in this semiconductor memory system, electrons are not injected from the drain portion into the channel portion. As a result, injection of electrons into the floating gate portion is prevented at the unselected memory cell. In addition, by roughly equalizing the level of the seventeenth voltage to the level of the reference voltage, a common source can be utilized.